Espressif Systems /ESP32-C6 /PARL_IO /RX_CFG0

Write 0 to select eof generated manchnism by configured data byte length. Write 1 to select eof generated manchnism by external enable signal.

Write 1 to start rx global data sampling.

Configures rx receieved data byte length.

Write 1 to enable software data sampling.

Pulse submode selection. 0000: positive pulse start(data bit included) && positive pulse end(data bit included) 0001: positive pulse start(data bit included) && positive pulse end (data bit excluded) 0010: positive pulse start(data bit excluded) && positive pulse end (data bit included) 0011: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 0100: positive pulse start(data bit included) && length end 0101: positive pulse start(data bit excluded) && length end 0110: negative pulse start(data bit included) && negative pulse end(data bit included) 0111: negative pulse start(data bit included) && negative pulse end (data bit excluded) 1000: negative pulse start(data bit excluded) && negative pulse end (data bit included) 1001: negative pulse start(data bit excluded) && negative pulse end (data bit excluded) 1010: negative pulse start(data bit included) && length end 1011: negative pulse start(data bit excluded) && length end

Write 0 to sample data at high level of external enable signal. Write 1 to sample data at low level of external enable signal.

Rx data sampling mode selection. 000: external level enable mode 001: external pulse enable mode 010: internal software enable mode

Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable sampling data on the falling edge of rx clock.

Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.

Rx data bus width selection. 100: bus width is 1 bit 011: bus width is 2 bits 010: bus width is 4 bits 001: bus width is 8 bits 000: bus width is 16 bits

Write 1 to enable soft reset of async fifo in rx module.